The present invention relates generally to cleaning methods used in the fabrication of semiconductor devices. More particularly, the present invention pertains to protecting at least one material while removing at least one other material from a workpiece during the fabrication of a semiconductor device.
The fabrication of semiconductor devices often involves providing materials over a substrate and shaping those materials through processes such as photolithography and etching. In the current application, the term xe2x80x9csubstratexe2x80x9d or xe2x80x9csemiconductor substratexe2x80x9d will be understood to mean any construction comprising semiconductor material, including but not limited to bulk semiconductive materials such as a semiconductor wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). Further, the term xe2x80x9csubstratexe2x80x9d also refers to any supporting structure including, but not limited to, the semiconductive substrates described above. Moreover, it is understood that a semiconductor device may comprise conductive and insulative materials as well as a semiconductive material. While etching a semiconductor device, more than one type of material included as part of that device may be exposed to the etching environment, although it may not be desirable to etch all of the exposed materials at the same rate. In fact, some sort of etch selectivity is often preferable.
One example in which etch selectivity is desired involves processing a silicon wafer serving as the substrate, wherein processing is for purposes of constructing a memory device. A doped oxide can be deposited over the silicon substrate using methods known in the art. This doped oxide could be a tetraethylorthosilicate (TEOS) based glass, boropnosphosilicate glass (BPSG), borosilicate glass (BSG), phosphosilicate glass (PSG), an arsenic-doped silicon oxide, or some other doped oxide. For purposes of clearly explaining the current invention and its background, it is assumed that BPSG is deposited over the silicon substrate. At least one opening is then formed through the BPSG down to the substrate. This opening may be formed using an etch process as guided by a patterned mask layer over the BPSG. Again, such masking, patterning, and etching processes are known in the art. The resulting patterned BPSG layer allows for a conductive layer to be subsequently deposited, wherein the remaining BPSG portions electrically isolate the conductive material from the substrate, while the opening in the BPSG allows for electrical communication between the conductive material and the substrate. Because this opening allows for electrical contact between different layers, the opening itself is often referred to as a xe2x80x9ccontactxe2x80x9d both in the art and in this specification.
However, before such a conductive layer is deposited, conditions may be present that would interfere with electrical communication between the silicon substrate and the conductive layer to be deposited. For example, once a contact has been etched through the BPSG down to the silicon substrate, the uncovered silicon may be exposed to an oxidizing environment. Such an occurrence may take place in the form of cleaning an organic contaminant from the in-process device. In the presence of sufficient energy, such as thermal energy or that derived from a plasma ambient or an oxidizing liquid ambient, the exposed silicon reacts to form a silicon oxide, such as SiO2. Because the oxide is formed from a chemical reaction with an integral portion of the in-process device, the oxide may be referred to as a xe2x80x9cnativexe2x80x9d or xe2x80x9cchemicalxe2x80x9d oxide that has been xe2x80x9cgrownxe2x80x9d or formed. This is in contrast to a deposited oxide, wherein a deposition process, such as chemical vapor deposition (CVD), provides an oxide layer that is discrete from the in-process device""s previously existing structures. The BPSG layer mentioned above is an example of a deposited oxide. In providing an oxide in this manner, a dopant is often added to the ambient during the deposition process and ends up incorporated as part of the oxide. On the other hand, xe2x80x9cnativexe2x80x9d or xe2x80x9cchemicalxe2x80x9d oxides are undoped. Further, such oxides are electrical insulators. Accordingly, if any such oxide is allowed to remain at the bottom of the contact, it will hinder electrical communication between the substrate and a subsequently deposited conductive material.
As a result, in-process devices at this stage of fabrication often undergo cleaning steps to remove the native oxide at the bottom of the contact prior to depositing conductive material. One exemplary cleaning process known in the art concerns the use of solutions including hydrofluoric acid (HF). Either through immersion, spraying, vapor treatment, or other methods, the native oxide of the in-process device is exposed to and etched by the HF solution. The HF cleaning may be performed before, after, or between other cleaning steps performed with other solutions, such as an RCA clean, to provide a hydrogen passivated, hydrophobic, oxide-free surface.
Unfortunately, while HF etches the native oxide from the bottom of the contact, it also etches other oxides, including the deposited BPSG that defines the contact. In fact, a standard HF cleaning solution containing 300 parts H2O to 1 part HF etches BPSG over native oxide at an etch ratio of 10:1. The result is that the contact""s diameter is increased. Widening the contact is detrimental to semiconductor device fabrication, as the contact may be near conductive structures such as the conductive electrode of a capacitor. Because the opening will also be filled with a conductive material, a wider contact means that the two conductive elements will be closer, and the likelihood of a short between the two will therefore be increased, especially in the event of a misalignment in the fabrication process. This is even more of a problem if other processes also widen the contact. In fabricating a dynamic random access memory (DRAM), current process flows call for a contact that is 0.25 microns in diameter and is laterally spaced from a capacitor plate by only about 0.06 to 0.08 microns. Accordingly, any improvements that allow for less of an increase in the contact""s diameter are appreciated. In addition, there is a constant need in the industry to fabricate ever-smaller devices in order to maximize the efficient use of the wafer""s surface area. This need can be achieved by shrinking the dimension of features, such as the contact diameter. It follows that, once a feature""s dimension has been established, it is desired to avoid processes that may increase that dimension. Further, etching the BPSG will also reduce the vertical thickness of the BPSG layer. At current device sizes, reduction in thickness is not as critical a problem as the increase in contact diameter. Nevertheless, thinning the BPSG may be undesirable in certain circumstances. Thus, for these reasons as well as others, those skilled in the art look for ways to eliminate or at least reduce the widening of the contact in the BPSG that occurs while cleaning the bottom of the contact.
The use of other cleaning agents with a more favorable etch selectivity is one way to do so. One cleaning solution known in the industry comprises 30% ammonium fluoride by weight, 1% phosphoric acid, and 69% H2O. This solution has an etch selectivity ratio of 1.5:1. still in favor of BPSG. One vendor identifies this solution as xe2x80x9cQE II.xe2x80x9d Another cleaning solution, comprising 30% ammonium fluoride by weight, 3% phosphoric acid, and 67% H2O, has an etch selectivity ratio of 1:1. This solution is sometimes identified as xe2x80x9cSuper Q.xe2x80x9d
Another way to improve etch selectivity is to include an etch retardant in the etching/cleaning solution. Without limiting this or any other invention, it is believed that doing so creates competing reactions, with the etch retardant passivating the BPSG and the etchant etching the BPSG and other oxides, that results in a better etch selectivity in favor of undoped native oxide as opposed to doped deposited oxide. One such solution combines HF; H2O; and a component identified as (R)4NOH, wherein R=(C1-C20)alkyl and is preferably tetra ethyl ammonium hydroxide (TEAH) or tetra methyl ammonium hydroxide (TMAH). This chemical is addressed in greater detail in U.S. Pat. No. 5,783,495 by Li et al. and assigned to Micron Technology, Inc. BPSG/native oxide selectivity ratios based on Li""s teachings are known to range from 0.5:1 to 2:1. Another selective oxide etchant (identified by one vendor as SOE) achieves a BPSG/native oxide etch selectivity ratio of 0.8:1 using a combination of about 94% glycol by weight, about 5% ammonium fluoride, and about 1% iminodiacetic acid. Iminodiacetic acid is an iminopolyearboxylic acid and, more generally, an iminocarboxylic acid. Iminodiacetic acid may be identified by a molecular formula C4H7NO4, while a linear formula for iminodiacetic acid is HN(CH2CO2H)2. An exemplary structure for iminodiacetic acid follows. 
While these methods are useful in fabrication of semiconductor devices as well as other workpieces, there is nevertheless a constant need in the art to further reduce the amount of etching experienced by one type of oxide during a time in which another type of oxide is being etched. More generally, it is desired in the art to reduce the effect of a process on one material while that process acts upon another material.
Accordingly, the present invention provides for modifying a material in relation to a processing step. In some exemplary embodiments, the surface of a workpiece""s doped deposited oxide is passivated before exposing it to an etchant. In more specific embodiments of this type, a silicon wafer having a patterned doped oxide deposited thereon is dipped into an etch retardant prior to dipping the wafer in a solution containing both the etch retardant and an oxide etchant.
Other exemplary embodiments concern a passivation process preceding a cleaning step, wherein the effects of the combined passivation/cleaning steps define a xe2x80x9cbest fitxe2x80x9d line on a chart displaying the change in the dimension of a workpiece""s feature as a function of etch time. This line has a lower Y-axis intercept than does a line depicting the effect of the cleaning process without the exemplary passivation process, thereby indicating a preferable reduction in the amount of initial etching of the workpiece.
Still other embodiments encompass other prepassivation methods, postpassivation methods, and solutions and systems used therefore.